1. Field of the Invention
The present invention relates to dynamic memories, and more particularly to dynamic memories including dummy or reference cells.
2. Discussion of the Related Art
FIG. 1 partially represents such a dynamic memory that includes a plurality of memory cells, each including an N-channel MOS transistor MN or MN' to connect a capacitor C between a reference potential, such as ground, to a bit line BL or BL'. The cells are disposed in columns, corresponding to the bit lines BL and BL', and in rows. The columns are grouped by pair. Hereinafter, an "even" element is an element associated with any column of a pair, and an "odd" element is an element associated with the other column of the pair.
An even row of cells includes cells MN/C that are connected only to the even bit lines BL. An odd row of cells includes cells MN'/C that are connected only to the odd bit lines BL'. The gates of transistors MN or MN' of a row are connected to a selection line RW or RW', respectively.
The lines BL and BL' of a pair of columns are connected to a high voltage Vdd through P-channel MOS transistors, MP1 and MP1', respectively, and to ground through N-channel MOS transistors, MN1 and MN1', respectively. The gates of transistors MP1 and MP1' are connected to a precharge line P, and the gates of transistors MN1 and MN1' are connected to a write line W. Each pair of columns is associated with specific lines P and W to select the pair of columns. Additionally, each pair of lines BL and BL' is connected to the input of a comparator 70.
In the rectangle 72 drawn in dotted lines are represented so-called dummy or reference even and odd rows of cells. These reference cells are identical to the preceding cells, except that their capacitance, C/2, has half the value of capacitors C. The transistors of the even row of reference cells are labeled MND, and their gates are connected to a selection line RWD. The transistors of the odd row of reference cells are labeled MND', and their gates are connected to a selection line RWD'.
To write a "0" in a cell, the corresponding line RW or RW' and line W of the corresponding column pair are activated. Lines BL and BL' go to 0 and the capacitor C of the enabled cell is discharged.
To write a "1" in a cell, the corresponding line RW or RW' and the line P of the corresponding column pair are activated. The voltage on lines BL and BL' goes to Vdd and the capacitor C of the enabled cells is charged at voltage Vdd, at approximately the threshold voltage of transistors MN or MN'.
Prior to reading a cell, capacitors C/2 of the reference cells are discharged. This can be achieved by writing a series of "0" in these cells. Then, to read the memory cell, for example an even cell, lines BL and BL' of the corresponding pair of columns are first precharged at voltage Vdd by activating the associated line P. Lines BL and BL' have high value capacitors that are thus charged at voltage Vdd. Then, the selection line RW of the even row including the even cell to be read is activated simultaneously with selection line RWD' of the odd reference cells. Thus, a capacitor C is connected to line BL, and a capacitor C/2 is connected to line BL'. Since capacitor C/2 was previously discharged, a charge is transferred from line BL' to the reference capacitor C/2. The capacitance of line BL' has a high value as compared with the value of capacitor C/2, and the voltage on this line drops by approximately 100 mV only.
If the capacitor C of the cell to be read is charged, that is, if the cell is at "1", the state of line BL does not change. Thus, the voltage on line BL' is lower than the voltage on line BL, and comparator 10 switches to a first state indicating that the cell that is read is at "1".
If the capacitor C of the read cell is discharged (the cell is at "0"), a charge is also transferred from line BL to capacitor C. Since the value of capacitor C is twice the value of capacitor C/2 of the reference cell, the voltage drop on line BL is twice as high as that on line BL'. Thus, the voltage on line BL becomes lower than the voltage on line BL' and comparator 10 switches to a second state indicating that the cell that is read is at "0".
One of the difficulties for the manufacturing of such a dynamic memory lies in the implementation of a sufficiently precise ratio between capacitors C and capacitors C/2. In technologies intended to fabricate dynamic memories only, studies and tests have overcome this difficulty by establishing design rules for the capacitors C and C/2. However, when these rules are applied to distinct technologies, unlike results are obtained, to such an extent that capacitors C and C/2 may have close values. This situation is particularly impairing if it is desired to include dynamic memories in various circuits, that are not exclusively intended to serve as memories, such as circuits for the processing of signals, since these various circuits can be fabricated in a plurality of distinct technologies to which the same design rules of capacitors cannot be applied.